Novel Study of Influence of Gate Layout Geometries on RF Cascode nMOSFETTransit Frequency

The influence of different gate-layout geometries on a cascode nMOSFET’s transit frequencywas studied. Four cascode nMOSFET transistors were fabricated using different interdigitized gate layout geometries. Furthermore, a conventional cascode transistor was fabricated in order to compare it with the proposed interdigitized layouts. The transistors were measured on-wafer and the maximum transit frequency was extracted from the de-embedded transistor parameters. The de-embedding fixtures were designed for these cascode transistors in order to be able to supplyDCbias to the gates, drain, and source.The interdigitized cascode with single-sided contacts in a multi-finger polysilicon gate was found to have the highest transit frequency. This implies that the parasitic parallel capacitance from gate to substrate has a greater effect on the transit frequency than the gate resistance in a interdigitated cascode transistor. The cascode transistors were fabricated using a three-metal-layer, double poly 0.35 m CMOS process.